/* --------------------------------------------------------------------- */
declaration
  dataunit : bit;
  functions
    SRAM_TEST
  ;
  Manufacturers
    RAM
  ;
  Devices
    SRAM_64KBIT
  ;
		/*  ΥΝΝΝΝΈΥΝΝΝΝΈ        */
  chips =  NC,  /* [³ 1     28 ³] VCC   */
	  A12,  /* [³ 2     27 ³] WE    */
          A7 ,  /* [³ 3     26 ³] CE2   */
	  A6 ,  /* [³ 4     25 ³] A8    */
	  A5 ,  /* [³ 5     24 ³] A9    */
          A4 ,  /* [³ 6     23 ³] A11   */
	  A3 ,  /* [³ 7     22 ³] OE    */
	  A2 ,  /* [³ 8     21 ³] A10   */
	  A1 ,  /* [³ 9     20 ³] CE1   */
	  A0 ,  /* [³ 10    19 ³] D7    */
	  D0 ,  /* [³ 11    18 ³] D6    */
	  D1 ,  /* [³ 12    17 ³] D5    */
	  D2 ,  /* [³ 13    16 ³] D4    */
	  GND,  /* [³ 14    15 ³] D3    */	  
		/*  ΤΝΝΝΝΝΝΝΝΝΝΎ        */
	D3, D4, D5, D6, D7, CE1, A10, OE, A11, A9, A8, CE2, WE, VCC
  ;

  $v3 = VCC;

endd
/* -----------------------------------------------------------------------
 * init() ---> inital processing
 * ----------------------------------------------------------------------- */
int  init()
{
  @Vout  1,  5.0;
  @Vout  2,  5.0;
  @Vout  3,  5.0;
  @Out   GND, @G;
  @Delay 10, @Ms;
  
  @Out   NC,      @W;
  @Out   A[0..12],@W;
  @Out   D[0..7], @Z;
  @Out   WE,      @W;
  @Out   CE1,     @W;
  @Out   CE2,     @W;
  @Out   OE,      @W;

  @Out   NC,      @L;
  @Out   A[0..12],@L;
  @Out   WE,      @H;
  @Out   CE1,     @L;
  @Out   CE2,     @H;
  @Out   OE,      @H;

  @Out   VCC,     @O;  

  @Delay 100, @Ms;
}
/* -----------------------------------------------------------------------
 * MAIN Porgram
 * ----------------------------------------------------------------------- */
int  main()
{
  int  tmp, data;
  int  i, j;
   
  init();
  tmp = data = 0;  

  @Display 24, 14, "Current : ";

  for(i=0; i<0x2000; i++)
  {
     @Display  34, 14, i, @D;   
     for(j=0; j<2; j++)
     {
       if(j == 0) data = 0x55;
       else       data = 0xaa;
/* ------------------------ Write cycle ------------------- */
       @Out A[0..12], i;
       @Out D[0..7],  @W;
       @Out D[0..7],  data;
       @Out WE,       @L;
       @Out WE,       @H;
       @Out D[0..7],  @Z;       
/* ------------------------ Read cycle -------------------- */     
      @Out OE, 	      @L;
      @In D[0..7],    tmp;
      @Out OE,        @H;
      if(tmp != data) @Exit;
    }
  }
}